The semi-conductor industry has burgeoned in recent years. The electronics revolution occasioned by the semiconductor, and, specifically, the transistor and integrated circuit, has impacted significantly upon the consumer, industrial, governmental, and defense markets.
In many of the applications to which such electronic components are put, it is essential that they be 100% accurate in their operation and that all portions of the component function properly. In other applications, however, an IC need not meet as close tolerances as are necessary in more sophisticated applications and need not be completely functional in all circuitry paths.
For various reasons, the manufacturing process for integrated circuits, as in the case of other manufacturing processes, will produce units of different quality. For this reason, it is necessary to test the units not only to answer the relatively unsophisticated question of whether they are operable or not, but also to classify the units by degree of operability and quality. The best units can be used in applications wherein close tolerances and accuracy are essential. Those of lesser quality and integrity still might, however, be able to be used in other less demanding applications.
To this end, various high speed testing devices have been developed in order to ascertain the quality of function and integrity of various IC chips. Typically, such testers can perform testing upon in excess of three units per second. It is, therefore, necessary to provide handling equipment capable of feeding units to the test site and conveying those units away from the test site at as least as rapid a rate.
Various types of high speed handlers have been developed to solve this problem. Because of the high speed of operation, however, difficulties exist in devising structures which minimize the potential for jamming of the chip carriers as they are moved along a path through the input section of the handler, through the test site, and through the output section of the handler. The possibility of jamming is particularly likely at locations where the direction of movement of the chip carriers is changed. It is, therefore, particularly important that any handler designed to handle chip carriers at a high speed rate include structures for inhibiting canting and skewing of the carriers as they are passed therethrough.
An essential characteristic of any handler must be that it feeds chip carriers to the test site in a proper orientation. Typically, chip carriers are relatively planar in construction and have contact pads extending to only one of two oppositely facing planar surfaces. It is, therefore, essential that the proper face of the carrier be placed into engagement with the contacts at the test site in electronic communication with the tester.
In order to facilitate the proper orientation of the carriers at the test site, they must be fed into a handler with a given orientation. The handler must, thereafter, assure that, as the carriers pass through the various conveying means to the test site, they will not become inverted so that the contact pads will not engage the contacts at the test site. Additionally, because certain pins at the test site are specifically designated for engagement with certain of the contact pads, it is necessary that the handler conveying structure assure that the chip carriers are not rotated any measure about an axis extending perpendicularly to planes defined by the generally oppositely facing surfaces of the carrier. The operator of the tester can, thereby, feel relatively certain that testing of the carriers will be properly conducted and achieve a high measure of validity.
The operation of many chip carrier handlers requires that, at various stages, the machine be able to sense the presence of a carrier at a particular station. Illustrative of this requirement is the typical test site wherein, as a chip carrier is moved into position, its presence will be sensed so that a plunger will move the carrier into position wherein the contact pads engage the pins at the test site. It is understood, of course, that other stations exist with respect to which it is essential that the machine sense the presence of a carrier before some function can be initiated.
One type of device which is frequently used in order to sense the presence of a carrier at a particular station is an optical arrangement which includes a light emission device (LED) and a photosensor. The LED and sensor are positioned relative to one another on opposite sides of the station at which it is desired to sense the presence of a chip carrier. The LED and sensor are positioned so that the LED normally illuminates the sensor. When a carrier is in the station, the light beam illuminating the sensor will be broken, and electrical circuitry will actuate switches to indicate the presence of a carrier at the station. When the station is at the test site, the plunger will, thereby, be actuated to move the carrier so that the contact pads will engage the pins so that testing can be performed.
Frequently, it is desirable that, prior to testing, the chips be elevated or lowered to temperatures at least at which they will be maintained when subsequently installed in a device in which they are intended to be used. With respect to heated environmental operations, chips are frequently exposed to temperatures in excess of 100.degree. Centigrade. In order to ensure operation under aggravated temperature conditions, test temperatures are often elevated well in excess of 100.degree. Centigrade.
Under temperatures of this degree, however, LED sensing devices cannot operate properly and for extended periods of time. Consequently, uniquely different devices for sensing the position of a chip carrier at a particular station must be devised.
It is to these desirable characteristics and problems in the prior art that the invention of the present application is directed. The present invention is a handler which not only processes chip carriers at high speeds and limits the likelihood of misorientation, but it also processes the carriers such that jamming is minimized. Additionally, it is structured so that, if jamming does occur, jams can be cleared easily and expeditiously. Finally, it includes new means for sensing depositing of a chip carrier at a particular station. It, thereby, eliminates problems previously encountered because of inoperability of LED devices occasioned by the application of heat.